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| (R) TDK SEMICONDUCTOR CORP. 73M2901CL V.22bis Single Chip Modem May 2002 DESCRIPTION The 73M2901CL is a single-chip modem that combines all the controller (DTE) and data pump functions necessary to implement an intelligent V.22bis data modem. It is adequately suited for embedded applications where a data return channel is needed through the telephone network such as Set top Box, Point of Sale Terminal, Automatic Teller machine, Hand Held Communication Device and Smart Card Reader. This device is based on TDK Semiconductor's implementation of the industry standard 8032 microcontroller core with a proprietary Multiply/ ACcumulate (MAC) coprocessor; Sigma-Delta A/D and D/A converters (CODEC); and an analog DAA drivers. The ROM and RAM necessary to operate the modem are contained on the device. Additionally, the 73M2901CL provides an on-chip oscillator and hybrid. FEATURES * * * * True one chip solution for embedded systems Low power As low as 9.5mA operating with standby and power down mode available Power supply operation from 3.6V to 2.7V Data speed: V.22bis - 2400bps V.22/Bell212 - 1200bps V.21/Bell103 - 300bps V.23 - 1200/75bps (with PAVI turnaround) Bell202 - 1200bps Bell202/V23 4-wire operations International Call Progress support FCC68, CTR21, JATE, etc. Worldwide Caller ID capability Type I and II support EIA 716 compliant DTMF generation and detection On chip hybrid driver Blacklisting capability Line-In-Use and Parallel Pick-Up (911) detection capability Manufacturing Self Test capability Packaging: 32 pin PLCC / 32 pin TQFP / 44 pin LQFP * * * * * * * * BLOCK DIAGRAM 73M2901CL V.22bis Single Chip Modem HARDWARE DESCRIPTION The 73M2901CL is designed to operate from a +3.6 to +2.7 volt supply with low power consumption (~30mW @ 3.0 volts). The modem supports automatic standby idle mode. The modem will also accept a request to power down from the DTE via hardware control. No additional major components are required to complete the modem core logic. The modem provides direct firmware LED support via port pins. HARDWARE FEATURES * * * * * * Fully self-contained. "AT" Command interpreter and data pump User pins available Synchronous serial data I/O available Asynchronous serial port On-chip hybrid and line driver. Autobaud capability from 300bps to 9600bps INTERRUPT PINS The external interrupt sources, '75 and 5,1*, come from dedicated input pins of the same name. DTR informs the 73M2901CL that the host has requested the 73M2901CL perform a specific function. The function of '75 can be changed by "AT" commands (described in full in the TDK 73M2901CL User's Guide). RING is used to inform the 73M2901CL that the external DAA circuitry has detected a ring signal. In addition, sending any character on the TXD line also generates an internal interrupt. CRYSTAL OSCILLATOR LOW POWER MODE The TDK 73M2901CL supports a low power standby mode. If the low power standby option is enabled the 73M2901CL will go into a power saving mode when idle. The oscillator will be running, clocks will be supplied to the UART, timers and interrupt blocks; The TDK 73M2901CL single chip modem can use an external 11.0592 MHz reference clock or can generate a clock using only a crystal and two capacitors. If an external clock is used, it should be applied to OSCIN. but no clocks will be supplied to the CPU. Instruction processing and activity on the internal busses is halted. Normal operation is resumed when an interruption such as assertion of '75 or 5,1*, a character is sent to the 73M2901CL TXD input, or a reset occurs. ANALOG LINE / HYBRID INTERFACE The 73M2901CL provides a differential analog output (TXAP and TXAN) and a single-ended analog input (RXA) with internal A/D and D/A converters. A driver is provided for an internal hybrid function. The internal hybrid driver is capable of driving an external load matching impedance and a linecoupling transformer. The internal hybrid/line driver senses the load and adapts itself to its requirements. The 73M2901CL provides firmware control for a hook relay driver (5(/$<) as well as interrupt support for a ring detect opto-coupler (5,1*). POWER SUPPLY Power is supplied to the 73M2901CL via the VPD and VPA pins. The 73M2901CL is designed for a single +3.6 to +2.7 volt supply and for low power consumption (~30mW @ 3.0 volts). Ground is supplied to the 73M2901CL via VND and VNA pins. The 73M2901CL has been designed with separated analog and digital supplies to insure the best performance of the part by using different filtered power supplies. It is recommended that separate locally bypassed traces be used to apply power to the analog supply VPA and the digital supply VPD. 2 73M2901CL V.22bis Single Chip Modem SPECIFYING A CRYSTAL The manufacturer of a crystal resonator verifies its frequency of oscillation in a test set-up, but to ensure that the same frequency is obtained in the application, the circuit conditions must be the same. The TDK 73M2901CL modem requires a parallel mode (anti-resonant) crystal, the important specifications of which are as follows: Mode: Frequency: Frequency tolerance: 50 ppm at initial temperature. Temperature drift: An additional 50 ppm over full range. Load capacitance: ESR: Drive level: 18pF or 20pF 75 max. Less than 1mW. Parallel (anti-resonant) 11.0592 MHz Crystals with low ESRs may oscillate at higher than specified voltage levels. RESET A reset is accomplished by holding the RESET pin high. To ensure a proper power-on reset, the reset pin must be held high for a minimum of 3s. At power on, the voltage at VPD, VPA, and RESET must come up at the same time for a proper reset. The signals '&', &76 and '65 will be held inactive for 25ms, acknowledging the reset operation, within a 250ms time window after the reset-triggering event. The 73M2901CL is ready for operation after that 250ms window and/or after the signals '&', &76 and '65 become active. ASYNCHRONOUS AND SYNCHRONOUS SERIAL DATA INTERFACE The serial data interface consists of the TXD and RXD data paths (LSB shifted in and out first, respectively); and the TXCLK and RXCLK serial clock outputs associated with the data pins; &76/576 flow control; '&', '65 and '75. In synchronous mode, the data is passed at the bit rate (tolerance is +1%, -2.5%). The peak voltage level of the oscillator should be checked to assure it will not violate the maximum voltage levels allowed on the oscillator pins. A resistor in series with the crystal can be used, if necessary, to reduce the oscillator's peak voltage levels. PIN DESCRIPTIONS POWER PIN DESCRIPTION PIN NAME VPA VNA VPD VND 32 pin PLCC 15 21 6, 25, 29 5, 22, 26 32 pin TQFP 10 16 2, 20, 25 1, 17, 22 44 pin LQFP 16 22 2, 12, 27, 33 11, 24, 44, 28 TYPE I I I I DESCRIPTION Positive analog voltage (Analog supply) Negative analog voltage (Analog ground) Positive digital voltage (Digital supply) Negative digital voltage (Digital ground) ANALOG INTERFACE PIN DESCRIPTION PIN NAME RXA TXAN TXAP VBG VREF 32 pin PLCC 20 16 17 19 18 32 pin TQFP 15 11 12 14 13 44 pin LQFP 21 17 18 20 19 TYPE I O O O O DESCRIPTION Receive Analog input Transmit Analog - output Transmit Analog + output Analog Band Gap voltage reference (0.1F to VNA). This pin must not be connected to external circuitry other than the decoupling capacitor. Analog reference voltage (0.1F to VNA) 3 73M2901CL V.22bis Single Chip Modem DIGITAL INTERFACE PIN DESCRIPTION PIN NAME RESET RXCLK TXCLK TXD RXD USR10 32 pin PLCC 13 31 28 27 30 12 32 pin TQFP 9 27 24 23 26 8 44 pin LQFP 9 36 31 30 35 8 TYPE I O O I O I/O DESCRIPTION Reset Receive data synchronous clock Transmit data synchronous clock Serial data input from DTE Serial output to DTE Programmable I/O port. This pin optionally be used to control an external switch for external Line In Use circuitry. Programmable I/O port. This pin can optionally be used to control an external switch for caller ID operation. Request to send Clear to send Data set ready Data carrier detect Ring indicator Relay driver output Programmable I/O port USR11 576 &76 '65 '&' 5, 5(/$< USR20 11 10 9 8 7 4 3 1 7 6 5 4 3 32 31 29 7 6 5 4 3 43 40 38 I/O I O O O O O I/O EXTERNAL INTERRUPTS PIN DESCRIPTION PIN NAME 5,1* '75 32 pin PLCC 2 32 32 pin TQFP 30 28 44 pin LQFP 39 37 TYPE I I DESCRIPTION External interrupt - Line interface ring detection circuitry input External interrupt - DTE DTR signal input OSCILLATOR PIN DESCRIPTION PIN NAME OSCIN OSCOUT 32 pin PLCC 24 23 32 pin TQFP 19 18 44 pin LQFP 26 25 TYPE I O DESCRIPTION Crystal input for internal oscillator, also input for external source Crystal oscillator output 4 73M2901CL V.22bis Single Chip Modem ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage Pin Input Voltage (except OSCIN) Pin Input Voltage (OSCIN) Storage Temperature RATING -0.5V to +4.0V -0.5V to + 6.0V -0.5V to VPD + 0.5V -55C to 150C NOTE: This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum conditions for extended periods of time may affect reliability. RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage Oscillator Frequency Operating Temperature RECEIVER PARAMETER Carrier detect On Carrier detect Off Carrier Detect Hysteresis Receive Level Idle channel noise Input impedance Receive Gain Boost Max Input Level at RxA Total Harmonic Distortion (THD) CONDITIONS Tip and Ring Tip and Ring Tip and Ring Tip and Ring 0.2KHz - 4.0KHz RXA SFR 96.2h = 1 Vref=1.25V 1KHz 450mVpk on RXA THD=2 nd RATING 2.7V - 3.6V 11.0592MHz +/- 50ppm -40C to 85C MIN -43 -48 NOM MAX UNIT dBm0 dBm0 * * 2 -43 -70 150 18.8 0.587 rd dB -9 -65 19.8 0.658 -50 dBm0 dB k dB Vpk dB * 19.3 0.622 -70 and 3 harmonic * dBm0 refers to the TDK recommended line interface (8dB loss from transmit pins to the line and 5dB loss from the line to the receiver pin). Results may vary depending on the selected DAA components. 0dBm=0.775mVrms; dBm=10log(Vrms2/(1mW)(600)) 5 73M2901CL V.22bis Single Chip Modem TRANSMITTER PARAMETER CONDITIONS 550Hz (relative to carrier) 1800Hz (relative to carrier) 1300Hz 2225Hz/2100Hz High band tones Low band tones By step 1KHz sine wave at output (TXAP-TXAN) 1.5Vpk(2.7dBm) for Vref=1.25V nd rd THD=2 and 3 harmonic At output (TXAP-TXAN) 1KHz, 1.2KHz sine waves summed 2Vpk for Vref=1.25V -30dBm signal at VPA 300Hz-30KHz. Measured TXAP to TXAN MIN -5 -8 -11 -11 -12 -13.7 -0.3 NOM -3.5 -6.5 -10 -10 -11.5 -13.2 0 MAX -2 -5 -9 -9 -11 -12.7 0.3 UNIT dB dB dBm0 * dBm0 * dBm0 * dBm0 * dBm0 * ITU Guard tone power Calling Tone Answer Tone power DTMF Transmit power Gain adjust tolerance Total Harmonic Distortion (THD) -50 dB Intermod Distortion Each unwanted frequency component Sum of unwanted frequency components in pass band -33 dBm dB below low tone dB -20 Power supply rejection ratio 30 MAXIMUM TRANSMIT LEVEL PARAMETER QAM DPSK FSK DTMF (HIGH TONE) DTMF (LOW TONE) * CONDITIONS Vref=1.25V VPA=3.3V Vref=1.25V VPA=3.3V Vref=1.25V VPA=3.3V Vref=1.25V S13=$20, VPA=3.3V VPA=3.3V S85=80 Vref=1.25V S13=$20, S85=80 MIN NOM MAX -9.6 -7.4 -5.3 UNIT dBm0 dBm0 dBm0 dBm0 * * * -8 -9.7 -7 -8.7 * dBm0 * dBm0 refers to the TDK recommended line interface (8.5dB loss from transmit pins to the line and 3.5dB loss from the line to the receiver pin). Results may vary depending on the selected DAA components. 0dBm=0.775mvrms; dBm=20log(Vrms/(0.775mvrms) 6 73M2901CL V.22bis Single Chip Modem DC CHARACTERISTICS VCC=3.3V (Vdd stands for VPD and VPA) PARAMETER Input low voltage (except OSCIN) Input low voltage OSCIN Input high voltage (except OSCIN) Input high voltage OSCIN Output low voltage (except OSCOUT) Output low voltage OSCOUT Output high voltage (except OSCOUT) Output high voltage OSCOUT Input leakage current (except OSCIN) Input leakage current OSCIN SYMBOL VIL VIL VIH VIH VOL VOLOSC VOH VOHOSC IIH IIH IOL=4mA IOL=3mA IOH=-4mA IOH=-3mA Vss MIN -0.5 -0.5 0.7Vdd 0.7Vdd NOM MAX 0.8 0.2Vdd +5.5 Vdd+0.5 0.45 0.7 UNIT V V V V V V V V Vdd-0.45 Vdd-0.9 1 1 30 A A PARAMETER VBG VREF TXAP to TXAN offset CONDITIONS Vdd=3.3V Vdd=3.3V Vdd=3.3V, steady state MIN 1.19 1.19 NOM 1.25 1.25 MAX 1.31 1.31 50 UNIT V V mV DC SUPPLY CURRENT VDD = 2.7V (BATTERY EOL) PARAMETER Maximum Power supply, normal operation Maximum power supply Idle mode Maximum power supply Power down mode DC SUPPLY CURRENT VDD = 3.0V PARAMETER Maximum Power supply, normal operation Maximum power supply Idle mode Maximum power supply Power down mode SYMBOL IDD1 IDD2 IDD3 CONDITIONS 30pF/pin 30pF/pin 30pF/pin MIN NOM 10.6 1.1 MAX 11.9 1.7 10 UNIT mA mA A SYMBOL IDD1 IDD2 IDD3 CONDITIONS 30pF/pin 30pF/pin 30pF/pin MIN NOM 9.5 900 MAX 10.5 1500 10 UNIT mA A A 7 73M2901CL V.22bis Single Chip Modem DC SUPPLY CURRENT VDD = 3.3V PARAMETER Maximum Power supply, normal operation Maximum power supply Idle mode Maximum power supply Power down mode DC SUPPLY CURRENT VDD = 3.6V PARAMETER Maximum Power supply, normal operation Maximum power supply Idle mode Maximum power supply Power down mode SYMBOL IDD1 IDD2 IDD3 CONDITIONS 30pF/pin 30pF/pin 30pF/pin MIN NOM 13.4 1.4 MAX 15.5 2.0 10 UNIT mA mA A SYMBOL IDD1 IDD2 IDD3 CONDITIONS 30pF/pin 30pF/pin 30pF/pin MIN NOM 11.8 1.25 MAX 13.6 1.85 10 UNIT mA mA A 8 73M2901CL V.22bis Single Chip Modem FIRMWARE DESCRIPTION* An "AT" command interpreter provides command and configuration of the 73M2901CL. This provides the user a uniform interface to control the modem in embedded applications. The signal processing is performed to provide data to the DAC and process data from the A/D converter. A MAC hardware coprocessor is provided for computation. To provide maximum flexibility, the system host processor can access the internal RAM and Control Register space in the modem. This will allow the OEM user to modify parameters such as filter response, transmit levels through the AT command set using proprietary commands. The host processor can also access the modem I/O port pins, providing extended I/O capability. FIRMWARE REQUIREMENTS The modem always powers up in the idle (on hook) mode. "AT" commands are issued via the serial interface from the host. All modem configuration commands are received in this manner. The data modem firmware is contained in an internal ROM. The firmware will automatically enter a power saving idle mode if the modem is on hook and there are no incoming host commands. The modem automatically powers up upon receiving the next command. This power up sequence occurs without delay to the host. This function, while saving power, is transparent to the host processor and can be disabled by the host via an "AT" command. The host can also program the modem to power down via external pin (DTR) or via a firmware command. FIRMWARE FEATURES * * * * * "AT" command set Supports data standards through V.22bis Provides DAA control firmware (e.g. ring detect, hook control) Multinational Call progress support (FCC68, CTR21, JATE, etc.) Caller ID capability FSK demodulation (V23 or Bell202) DTMF demodulation Intra 1st/2nd ring CID data operation Post Line operation reversal CID data o o o o * On hook Line-In-Use detection support (No line seizure will occur when a Line-In-Use condition is detected) o o * Tip/Ring voltage sensing Quiescent line validation Off hook Parallel Pick-Up detection support (Line seizure will be aborted as soon as a Parallel Pick-Up condition is detected) Directly interfaces with standard V.24/EIA-232 bus drivers (3.3V inverted level) serial interface using the built in serial port and firmware control of port pins Provides tone generation and detection including four imprecise and four precise call progress detect filters with programmable frequency and detection threshold Blacklisting capability Long Space disconnect Inactivity timeout Host access to program RAM provided User programmable general purpose I/O * * * * * * * * Refer to the TDK 73M2901CL User Guide for a complete description of the software. 9 73M2901CL V.22bis Single Chip Modem TDK Semiconductor's 73M2901CL single chip modem includes all the basic modem functions. Programmable configuration options make this device highly adaptable to a wide variety of applications. Unlike digital logic circuitry, modem designs must contend with precise frequency tolerances and verify low-level analog signals, to ensure acceptable performance. Using good analog circuit design practices will generally result in a sound design. The crystal oscillator should be held to a 50ppm tolerance. The following recommendations should be taken into consideration when starting new designs. LAYOUT CONSIDERATIONS Good analog/digital design rules must be used to control system noise in order to obtain high performance in modem designs. The more digital circuitry present in the application, the more attention to noise control is needed. High speed, digital devices should be locally bypassed, and the telephone line interface and the modem should be located next to each other near where the telephone line connection is accessed. It is recommended that power supplies and ground traces should be routed separately to the analog and digital portions on the board. Digital signals should not be routed near low-level or high impedance analog traces. The 73M2901CL should be considered a high performance analog device. A 10F electrolytic capacitor in parallel with a 0.1F Ceramic capacitor should be placed between each VPD and VND pin as well as between VPA and VNA. A 0.1F ceramic capacitor should be placed between VREF and VNA as well as VBG and VNA. Use of ground planes and large traces on power is recommended. 73M2901CL DESIGN COMPATIBILITY The TDK 73M2901CL is an enhanced version of the TDK 73M2901C and has a number of new features. These parts are highly compatible with the earlier 73M2901 however special attention should be paid when changing an existing 73M2901 design to use the 73M2901CL. From a hardware standpoint, the key differences involve the User I/O pins USR10, USR11, the $65&+ pin and the HBDEN pin. An additional user I/O pin USR20 replaces the $65&+ pin on the 73M2901CL. This pin may remain safely connected to TXD as long as the host software does not reconfigure USR20 as an output (S104 bit0=0). The 73M2901CL contains a high efficiency low power hybrid driver. Due to this enhancement HBDEN is no longer required. This pin is an internal no-connect and can safely remain connected to its previous VPD or GND. The functions of USR10 and USR11 are related to Caller ID and Line In Use/Parallel Pickup support. Software enhancements to the 73M2901CL are typically achieved by the addition of new AT commands. The device can be considered a superset of the 73M2901. When converting a design to the 73M2901CL it is recommended that the user check the commands and register settings for backward compatibility to the earlier parts*. TELEPHONE LINE INTERFACE Transmit levels at the line are dependent on the interface used between the pins and the line. The internal hybrid line drivers eliminate the need for additional active circuitry to drive the line-coupling transformer. The analog outputs (TXAP and TXAN) can be connected directly to the transformer (with the required impedance matching series resistor or network) however some low cost transformers may be affected by the limited amount of DC current generated by the analog outputs (DC offset); hence it is recommended to use a coupling capacitor with those transformers to insure maximum performance. The line interface circuit shown on the following page represents the basic components and values for interfacing the TDK 73M2901CL analog pins to the telephone line. The values of these components have been calculated to minimize the transmission and reception path hybrid losses and are linked by the following equation: R15=0.242 x R13. * (refer to the TDK 73M2901CL User Guide for complete details) 10 73M2901CL V.22bis Single Chip Modem MODEM PERFORMANCE CHARACTERISTICS The curves presented in this data sheet define modem IC performance under a variety of line conditions typical of those encountered over Public Switched Telephone Network. BER VS. SNR This test represents the ability of the modem to operate over noisy lines with a minimum amount of data transfer errors. Since some noise is generated in the best dial up lines, the modem must operate with the lowest signal to noise ratio (SNR) possible. Better modem performance is indicated by test curves that are closest to the BER axis. A narrow spread between curves representing the four line parameters indicates minimal variation in performance while operating over a range of typical operating conditions. A DPSK modem will exhibit better BER performance test curves receiving in the low band (answer mode) than in the high band (originate mode). BER VS. RECEIVE LEVEL This test measures the dynamic range of the modem. Because signal levels vary widely over dial up lines, the widest possible dynamic range is desirable. The SNR is held constant at the indicated values as the Receive level is lowered from a very high to a very low signal level. The width of the bowl of these curves, taken at the BER break points is the measure of the dynamic range. RECOMMENDED SCHEMATIC ARRANGEMENT VCC3_3D 11.0592 MHz + C1 10uF RST R1 10K TXDB VCC3_3D C11 0.1uF + C12 10uF TXDB OSCIN OSCOUT C13 + 10uF 0.1uF R15 5.1K RXA 16 15 RXA 14 VBG 13 VREF 12 TXAP 11 10 9 RST C7 2901CL_TQFP32 1 2 3 4 5 6 7 8 0.1uF C8 0.1uF R23 NC R13 21K TXAN VCC3_3A + C9 22uF C10 0.1uF R2 2K TXAN U2 R28 120K 6 5 4 2 LDA110* VCC3_3D 1 RINGB/PPUB/LIUB/LREVB DCDB DSRB CTSB RTSB DCDB DSRB CTSB RTSB 4 U3 TLP627 R18 100 2 3 4 U4 TLP627 R16 100 HOOKB U11P2 2 3 LIUCHECKB U10P2 1 C20 0.1uF RXA_TAP C4 .082UF C20R29 4 1 671-8005 C14 TXAP C2 Y1 27pF OSCOUT C3 33pF ISOLATION BARRIER R17 475 T1P3 T1 3 2 VCC3_3D U1 J1 CON10 10 9 8 7 6 5 4 3 2 1 RXDB DTRB TXDB RIB DCDB DSRB CTSB RTSB VCC3_3 25 RXDB 26 27 DTRB 28 29 30 HOOKB 31 RIB 32 VCC3_3A R20 22K VND VPD DCD DSR CTS RTS USR11 USR10 C5 10uF VPD RXD RXCLK DTR USR20 RING RELAY RI TXCLK TXD VND N/C VPD OSCIN OSCOUT VND 24 23 22 21 20 19 18 17 VNA RXA VBG VREF TXAP TXAN VPA RESET + C6 1 0.1uF VCC3_3D VCC3_3 VCC3_3D [js1] 11 73M2901CL V.22bis Single Chip Modem TYPICAL USA APPLICATION SCHEMATIC PPU Circuit CID_COUPLED R4 13K R3 33K R5 13K Q3C 3 Q2C R6 27K 2 Q1B R7 1K 1 CMPT6429 Q2B 1 Q1 2N5087 Q1C 3 R21 100 OHMS A D2 CMR1F-04M D7 D3AD7A A A CMR1F-04M 12V C C D6 D5AD6A A A 22V 22V C F1 TR250-145 RAYCHEM POLYSWITCH J2 TIP1 RING 4 3 2 1 CON4 D2CR25 D3 Q3B 1 CMPT6429 3 Q3 2 Q2 Q3EQ2E ISOLATION BARRIER T1 3 2 CID_COUPLED C D1 4 1 A CLL5239B 9.1V 0.5W DAA_COM LIUDET R14 62K + C15 10uF DAA_COM R12 20K 2 R10 62K C16 1uF 671-8005 R19 20K R19Q14C C RING/LREVDET U2 6 5 4 2 LDA110* 1 4 DAA_COM 0.47UF 250V DAA_PLUS L1 NLC322522T-4R7M TIPL1 U3 TLP627 U10P2 LIUDET R8 75K CID coupling R23C22 E1 P3100EA70 TECCOR SIDACTOR + 1 TIPF1 1 1N4001 D8 C17 C17R11 RING/LREV detection R11 9.1K R11D5C C D5 4 2 - U5 Z602 L2 NLC322522T-4R7M RINGL2 R9 R9C19 9.1K RING/LREV detection 0.47uF 250V C19 3 1 4 U4 TLP627 U11P2 C18 0.15uF 250V 2 3 12 0 OHMS R22 2 3 73M2901CL V.22bis Single Chip Modem BER CURVES BER vs. SNR BER vs. Receive Level 13 73M2901CL V.22bis Single Chip Modem 32 PIN PLCC PIN-OUT PIN 1 2 3 4 5 6 7 8 NAME USR20 5,1* 5(/$< 5, VND VPD '&' '65 PIN 9 10 11 12 13 14 15 16 NAME &76 576 USR11 USR10 RESET NC VPA TXAN PIN 17 18 19 20 21 22 23 24 NAME TXAP VREF VBG RXA VNA VND OSCOUT OSCIN PIN 25 26 27 28 29 30 31 32 NAME VPD VND TXD TXCLK VPD RXD RXCLK '75 32 PIN TQFP PIN-OUT PIN 1 2 3 4 5 6 7 8 NAME VND VPD '&' '65 &76 576 USR11 USR10 PIN 9 10 11 12 13 14 15 16 NAME RESET VPA TXAN TXAP VREF VBG RXA VNA PIN 17 18 19 20 21 22 23 24 NAME VND OSCOUT OSCIN VPD NC VND TXD TXCLK PIN 25 26 27 28 29 30 31 32 NAME VPD RXD RXCLK '75 USR20 5,1* 5(/$< 5, 44 PIN LQFP PIN-OUT PIN 1 2 3 4 5 6 7 8 9 10 11 NAME N/C VPD '&' '65 &76 576 USR11 USR10 RESET N/C VND PIN 12 13 14 15 16 17 18 19 20 21 22 NAME VPD N/C N/C NC VPA TXAN TXAP VREF VBG RXA VNA PIN 23 24 25 26 27 28 29 30 31 32 33 NAME N/C VND OSCOUT OSCIN VPD VND N/C TXD TXCLK N/C VPD PIN 34 35 36 37 38 39 40 41 42 43 44 NAME N/C RXD RXCLK '75 USR20 5,1* 5(/$< N/C N/C 5, VND 14 73M2901CL V.22bis Single Chip Modem PACKAGE PIN DESIGNATIONS (Top View) 32-Lead PLCC 73M2901CLIH RXCLK 32-Pin TQFP 73M2901CLIGV RELAY USR20 RING VND RXD DTR N/C N/C N/C VPD 1 2 3 4 5 6 7 8 9 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 N/C VPD N/C TXCLK TXD N/C VND VPD OSCIN OSCOUT VND N/C DCD DSR CTS RTS USR11 USR10 RESET N/C VND 10 11 23 12 13 14 15 16 17 18 19 20 21 22 RI TXAN TXAP VREF VBG VPD VPA RXA 44-Pin LQFP 73M2901CLIGT 15 VNA N/C N/C N/C 73M2901CL V.22bis Single Chip Modem MECHANICAL DRAWINGS 32 Pin PLCC 73M2901CLIH 16 73M2901CL V.22bis Single Chip Modem 32 Pin TQFP 73M2901CLIGV 17 73M2901CL V.22bis Single Chip Modem 44 Pin LQFP 73M2901CLIGT ORDERING INFORMATION PART DESCRIPTION 73M2901CL 32-Pin Plastic Leaded Chip Carrier 73M2901CL 32-Pin Thin Quad Flat Pack 73M2901CL 44-Pin Quad Flat Pack ORDER NUMBER 73M2901CLIH 73M2901CLIGV 73M2901CLIGT PACKAGING MARK 73M2901CLIH 73M2901CLIGV 73M2901CLIGT No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that you are referencing the most current data sheet before placing orders. To do so, see our web site at http://www.tdksemiconductor.com or contact your local TDK Semiconductor representative. TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780, (714) 508-8800, FAX (714) 508-8877, http://www.tdksemiconductor.com 2001 TDK Semiconductor Corporation 05/24/02- V1.2 18 |
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